VOL Low Level Output Voltage
JEDEC – The voltage level at an output terminal with input conditions applied that, according to the product specification, will establish a low level at the output.
TI – The voltage level at an output terminal with input conditions applied that, according to the product specification, establishes a low level at the output.
VOL is tested with input conditions that should cause the output under test to be at a low level. The output then is forced to sink the required current, as defined in the data sheet, and the output voltage is measured. The test is passed if the voltage is less than VOL max. The input voltage levels used to precondition the device are VIL max and VIH min, as defined in the recommended operating conditions. See IOL low-level output current for further information.
Helpful Hint:
Inclusion of a VOL specification with a test condition of IOL = 100
mA is done primarily to indicate that the device has CMOS outputs instead of bipolar (npn or pnp) drivers. Bipolar output transistors typically are not able to swing the output voltages all the way to the power-supply rail or ground rail, even under no-load or lightly loaded conditions. If the outputs were bipolar, this test condition would not apply and is not included in the data sheet. If you see this specification, you can safely assume the outputs to be of CMOS construction.