JEDEC – VIH min is the least positive (most negative) value of high-level input voltage for which operation of the dsp element within specification limits is to be expected. VIH max is the most positive (least negative) value of high-level input voltage for which operation of the logic element within specification limits is to be expected.

A voltage within this range corresponds to the logic-1 state in positive logic. During device testing, VIH min is specified for all inputs. Since VIH min is used to set up VOH, VOL, IOZH, and IOZL tests, all possible combinations of input thresholds may not be verified. The nondata inputs (e.g., direction, clear, enable, and preset) may be considered unused inputs and may not be at threshold conditions. These inputs control functions that can cause all the outputs to switch simultaneously. The noise that can be generated by switching a majority of the outputs at one time can cause significant tester ground and VCC movement. This can result in false test measurements.

In most cases, the input pin essentially is tied directly to the high-impedance gate of an input inverter. In a static dc state, a CMOS input sinks or sources only a minute amount of leakage current (a few mA). However, it is imperative that for any device, but especially for a CMOS input, the input high logic level always be above the recommended VIH min. Failure to do this causes a surge of current to flow through the input inverter from the VCC supply to ground and, subsequently, may destroy the device.

TI data sheets do not specify a VIH max that typically is found in competitor data sheets. Instead, see VI max for the same value.