tPLH Propagation Delay Time, Low-Level to High-Level Output
JEDEC – The time interval between specified reference points on the input and output voltage waveforms with the specified output changing from the defined low level to the defined high level.
TI – The time between the specified reference points on the input and output voltage waveforms, with the output changing from the defined low level to the defined high level.
Propagation delay time, tPLH, is tested by causing a transition on the specified input that causes the designated output to switch from a low logic level to a high logic level. For example, the transition applied is 0 V to VCC or VCC to 0 V for AC devices and 0 V to 3 V or 3 V to 0 for ACT devices. Trip points used for the timing measurements and output loads used during testing are defined in the individual data sheets in the parameter measurement information section, typically found after the switching characteristics over recommended ranges of supply and operating free-air temperature table. Propagation delay time, tPLH, is not checked simultaneously with other outputs or with other recommended operating conditions. The time between the specified reference point on the input voltage waveform and the specified reference point on the output voltage waveform is measured.