th Hold Time
JEDEC – The time interval during which a signal is retained at a specified input terminal after an active transition occurs at another specified input terminal.
TI – The time interval during which a signal is retained at a specified input after an active transition occurs at another specified input.
NOTE: 1. The hold time is the actual time interval between two signal events and is determined by the system in which the digital signal operates. A minimum value is specified that is the shortest interval for which correct operation of the digital circuit is to be expected.
NOTE: 2. The hold time may have a negative value, in which case, the minimum limit defines the longest interval (between the release of the signal and the active transition) for which correct operation of the digital circuit is to be expected.
Hold time is tested by holding an input at a fixed logic level for the specified time after the transition of the other input (see Figure below). The device passes if the outputs switch to their expected logic levels and fails if they do not. Hold times are not checked simultaneously with other inputs or other recommended operating conditions. For additional information about hold time, refer to the TI application report; Metastable Response in 5-V Logic Circuits, literature number SDYA006.