Power Sequencing and Low Power Modes
In an effort to minimize power use with DSPs, many processors will use a lower core voltage source than the peripherals of the device. The Peripheral voltage for most processors will need to be in the 3.3 to 5 volt range since most logic and analog devices operate with these input and out put voltages. The Core voltage will often differ from one family of DSPs to another, but each data sheet will contain information on low power modes and power sequencing requirements.
Since many processors will have a separate core and peripheral voltage, a minimum of two separate power supplies must exist. TI typically does not require a specific sequence of startup of these power supplies, but it is recommended that these supplies power up in about the same time period. If one supply is powered up a significant time (>1 second) before the other, then an error is likely to occur.
Many TI DSPs have the ability to go into low power modes when at idle. These modes can be used to not only shut down peripherals, but also the clocks. In these modes, specific conditions or interrupts must be used to recover from the low power mode. These modes are configured in specific registers that are enabled through a hardware pin or external interrupt.