JEDEC – no definition offered

TI – This specification defines the range of clock frequencies over which a bistable device can be operated while maintaining stable transitions between logic levels at the outputs.

The fclock parameter is tested by driving the clock input with a predetermined number of pulses. The output then is checked for the correct number of output transitions corresponding to the number of input pulses applied. The output is loaded as defined in the data-sheet specifications.

Each output is individually tested and not checked simultaneously with other recommended operating conditions or propagation delays. For counters, shift registers, or any other devices for which the state of the final output is dependent on the correct operation of the previous outputs, fclock will be tested only on the final output, unless specified independently in the data sheet. Full functionality testing is not performed during fclock testing or fmax testing.

The fmax and fclock parameters are two sides of the same coin. The fclock parameter tells you, the user, how fast you can reliably switch the input to the device. The fmax parameter informs TI when to reject a device that fails to function below a minimum speed. If you are a device user, you should simply disregard the fmax specification and use the fclock specification.