Four pins, P1.7 - P1.4 have both I/O and JTAG functions on
the 20 and 28-pin MSP430F1xx devices. The default function for
these pins is the I/O function when the device is powered up.
When the Test pin is pulled high, these pins are selected as JTAG.
The FET tools for those devices puts these pins in JTAG mode when
using the interactive in-system debugger. Please see the FET tool
User`s Guide for information on releasing the pins from JTAG mode
while using the debugger.
Note: If external circuitry is attached to the shared pins the
interaction of the JTAG signals to the pins must be considered.
If the device will be programmed or debugged interactively in-system
via JTAG, consider what effect the circuitry will have. Take into
account if the circuitry will load or bias the shared pins and
thereby interfere with JTAG communications. Higher pin count devices
have dedicated JTAG pins used only for debug and programming.
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